R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 357

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.3
The SH-2A/SH2A-FPU is a 2-ILP (2-Instruction-Level-Parallelism) super-scalar pipelining
microprocessor. When two instructions are in the ID stage, two instructions can be executed
simultaneously (see figure 8.6).
However, parallel execution is not possible in the following cases:
• When resource contention occurs (described in 8.3.1)
• When waiting for the result of a previously issued instruction (described in 8.3.2)
• When register contention or flag contention occurs (described in 8.3.3)
• When a multi-cycle instruction is executed as a preceding instruction (described in 8.3.4)
• When a 32-bit instruction is executed as a preceding instruction (described in 8.3.5)
• In the case of an instruction that uses FPSCR, an FPU instruction, or an FPU-related CPU
• Delayed unconditional branch instruction at which a branch occurs, and delay slot (described
When IF stages are completed for two instructions without the occurrence of such contention, the
SH-2A/SH2A-FPU can perform parallel execution of the two instructions.
The above cases are described in the following subsections. Terms used in the descriptions are as
follows:
• Preceding instruction: Earlier instruction in the same slot
• Succeeding instruction: Later instruction in the same slot
• Previously issued instruction: Generic term for an instruction that has already been issued
ADD R2,R3
MOV.L @R0,R1
ADD R4,R3
FADD FR1,FR2
instruction (described in 8.3.6)
in 8.3.7)
Instruction Execution and Parallel Execution Capability
Figure 8.6 Example of Parallel Execution
IF
IF
ID
ID
IF
IF
EX
EX
ID
DF
MA
EX
E1
WB
E2
Rev. 3.00 Jul 08, 2005 page 341 of 484
SF
Section 8 Pipeline Operation
REJ09B0051-0300