R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 373

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

If the destination register of a double-precision arithmetic operation instruction is used as a source
register by the following instruction, if “n” of FRn is an odd number, latency will be reduced by 1
cycle (figure 8.46). However, latency will not be reduced if “n” of FRn is an even number (figure
8.47).
Floating-point load/store
instruction (double-
precision)
(FMOV DR0,DR2)
(latency 1 → latency 2)
Next floating-point
arithmetic operation
instruction (double-
precision)
(FADD DR2,DR4)
Floating-point arithmetic
operation instruction
(double-precision)
(FADD DR0,DR2)
(latency 8 → latency 7)
Next floating-point
load/store instruction
(single-precision)
(FMOV FR3,FR5)
Figure 8.46 Example of Latency Reduction with Double-Precision Arithmetic
Figure 8.45 Example of 1-Latency Instruction Immediately Preceding
Double-Precision Arithmetic Operation
IF
IF
IF
DF EX NA SF
—
DF E1 E1 E1 E1 E1 E1 E2 SF
Operation Instruction
—
IF
DF E1 E1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ E1 E2 SF
—
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Rev. 3.00 Jul 08, 2005 page 357 of 484
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Section 8 Pipeline Operation
DF EX NA SF
REJ09B0051-0300