R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 80

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Instruction Set
5.1.6
Table 5.8
CLRT
CLRMAC
LDBANK @Rm, R0
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDS
LDS
LDS
LDS.L
LDS.L
LDS.L
NOP
RESBANK
RTE
SETT
SLEEP
STBANK R0, @Rn
STC
STC
STC
STC
STC.L
STC.L
STC.L
Rev. 3.00 Jul 08, 2005 page 64 of 484
REJ09B0051-0300
Instruction
Rm, SR
Rm, TBR
Rm, GBR
Rm, VBR
@Rm+, SR
@Rm+, GBR
@Rm+, VBR
Rm, MACH
Rm, MACL
Rm, PR
@Rm+, MACH
@Rm+, MACL
@Rm+, PR
SR, Rn
TBR, Rn
GBR, Rn
VBR, Rn
SR, @- Rn
GBR, @- Rn
VBR, @- Rn
System Control Instructions
System Control Instructions
0000000000001000 0 → T
0000000000101000 0 → MACH, MACL
0100mmmm11100101 (Specified register bank entry)
0100mmmm00001110 Rm → SR
0100mmmm01001010 Rm → TBR
0100mmmm00011110 Rm → GBR
0100mmmm00101110 Rm → VBR
0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm
0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm
0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm
0100mmmm00001010 Rm → MACH
0100mmmm00011010 Rm → MACL
0100mmmm00101010 Rm → PR
0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm
0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm
0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm
0000000000001001 No operation
0000000001011011 Bank → R0 to R14, GBR,
0000000000101011 Delayed branch, stack area →
0000000000011000 1 → T
0000000000011011 Sleep
0100nnnn11100001 R0 → (specified register bank
0000nnnn00000010 SR → Rn
0000nnnn01001010 TBR → Rn
0000nnnn00010010 GBR → Rn
0000nnnn00100010 VBR → Rn
0100nnnn00000011 Rn - 4 → Rn, SR → (Rn)
0100nnnn00010011 Rn - 4 → Rn, GBR → (Rn)
0100nnnn00100011 Rn - 4 → Rn, VBR → (Rn)
Code
→ R0
MACH, MACL, PR
PC/SR
entry)
Operation
Cycles
9 *
1
1
6
3
1
1
1
5
1
1
1
1
1
1
1
1
1
6
1
5
7
2
1
1
1
2
1
1
T Bit
LSB
LSB
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
0
1
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A/
SH2A-
New
FPU
Yes
Yes
Yes
Yes
Yes