R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 230

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.4.30
Format
MOV
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
Description
Transfers the source operand to the destination. When the operand is stored in memory, the
transferred data can be a byte, word, or longword. Loaded data from memory is stored in a register
after it is sign-extended to a longword.
Rev. 3.00 Jul 08, 2005 page 214 of 484
REJ09B0051-0300
Rm,Rn
Rm,@Rn
Rm,@Rn
Rm,@Rn
@Rm,Rn
@Rm,Rn
@Rm,Rn
Rm,@–Rn
Rm,@–Rn
Rm,@–Rn
@Rm+,Rn
@Rm+,Rn
@Rm+,Rn
Rm,@(R0,Rn)
Rm,@(R0,Rn)
Rm,@(R0,Rn)
@(R0,Rm),Rn
@(R0,Rm),Rn
@(R0,Rm),Rn
MOV
Data Transfer
Abstract
Rm → Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → sign extension → Rn
(Rm) → sign extension → Rn
(Rm) → Rn
Rn – 1 → Rn, Rm → (Rn)
Rn – 2 → Rn, Rm → (Rn)
Rn – 4 → Rn, Rm → (Rn)
(Rm) → sign extension → Rn,
Rm + 1 → Rm
(Rm) → sign extension → Rn,
Rm + 2 → Rm
(Rm) → Rn, Rm + 4 → Rm
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Rm → (R0 + Rn)
(R0 + Rm) → sign extension → Rn
(R0 + Rm) → sign extension → Rn
(R0 + Rm) → Rn
MOVe data
Code
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
0110nnnnmmmm0110
0000nnnnmmmm0100
0000nnnnmmmm0101
0000nnnnmmmm0110
0000nnnnmmmm1100
0000nnnnmmmm1101
0000nnnnmmmm1110
Data Transfer Instruction
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—