R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 493

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

as a simplified compensation. (This compensation appears as the final item in the equation
introduced below.)
Based on the above, the number of cycles necessary to execute the entire instruction string is as
summarized below, in extremely simplified terms. If some portions of the string have
dependencies and others do not, separate calculations should be made for each portion and the
results added together.
• If Dependencies Exist Between Instructions
• If No Dependencies Exist Between Instructions
In this case, “number of instructions that cannon be executed in parallel” is the total number of
instructions that cannot be executed in parallel due to resource contention (in particular, memory
access instructions that immediately follow another memory access instruction), instructions using
more than one execution state, and 32-bit instructions
The final item compensates for the effects of parallel execution by reducing the number of
required cycles for the preceding instructions.
Example: If Dependencies Exist Between Instructions
The “latency” cycles for all instructions are added together, producing a total of eight cycles.
Example: If No Dependencies Exist Between Instructions
Required number of cycles = 1 + 3 + 2 + 1 – (4 – 2) ÷ 2
ROTCL
BAND.B
ROTCL
BAND.B
ROTCL
ADD
BAND.B
MULR
Required number of cycles = sum total of “latency” cycles of all instructions
Required number of cycles = sum total of “execution state” cycles of all instructions– (total
number of instructions – number of instructions that cannon be executed in parallel) ÷ 2
# imm, R0
# imm, @(disp12,R2)
R4, R0
R5
= 7 – 1 = 6 cycles
Rev. 3.00 Jul 08, 2005 page 477 of 484
Section 8 Pipeline Operation
REJ09B0051-0300