R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 490

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
Operation
• Single-Precision
Operation
• Double-Precision
Instruction Issuance
These instructions use the FPU arithmetic operation pipeline.
Parallel Execution Capability
Parallel execution of a double-precision FCMP instruction and the following instruction is not
possible.
Rev. 3.00 Jul 08, 2005 page 474 of 484
REJ09B0051-0300
FCMP
BT
FCMP
BT
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after four stages
– IF, DF, E1, E2. As the T bit is checked in E2, an instruction that references the T bit
immediately afterward is stalled for 2 cycles.
The CPU pipeline ends after four stages – IF, ID, EX, EX – and the FPU pipeline after five
stages – IF, DF, E1, E1, E2. As the T bit is checked in E2, an instruction that references the T
bit immediately afterward is stalled for 3 cycles.
IF
IF
IF
IF
IF
IF
IF
IF
ID
DF
—
—
ID
DF
—
—
EX
E1
—
—
EX
E1
—
—
E2
ID
DF
E1
—
—
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
E2
ID
DF
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline