R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 221

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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6.4.27
Format
LDS
LDS
LDS
LDS.L @Rm+, MACH
LDS.L @Rm+, MACL
LDS.L @Rm+,PR
Description
Store the source operand into the system register MACH, MACL, or PR.
Operation
LDSMACH(long m)
{
}
LDSMACL(long m)
{
}
LDSPR(long m)
{
}
LDSMMACH(long m)
{
MACH=R[m];
PC+=2;
MACL=R[m];
PC+=2;
PR=R[m];
PC+=2;
MACH=Read_Long(R[m]);
Rm,MACH
Rm,MACL
Rm,PR
LDS
Load to System
Register
Abstract
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
LoaD to System register
/* LDS Rm,MACH */
/* LDS Rm,MACL */
/* LDS Rm,PR */
/* LDS.L @Rm+,MACH */
Rev. 3.00 Jul 08, 2005 page 205 of 484
Code
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
Section 6 Instruction Descriptions
System Control Instruction
REJ09B0051-0300
Cycle T Bit
1
1
1
1
1
1

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