R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 461
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) Address Error Exception Handling
Instruction Type
Address error exception handling
Pipeline
Operation
An address error is accepted in the ID stage of an instruction, and processing from that ID stage
onward is replaced by the address error exception handling sequence.
The pipeline ends after seven stages: IF, ID, EX, EX, MA, MA, MA. Address error exception
handling is not a delayed branch. The IF stage of the branch destination instruction is started from
the slot containing the last MA stage of the address error exception handling.
Address error generation sources comprise those related to an instruction fetch, and those related
to a data read or write. See the hardware manual for details of generation sources.
Address Error Exception Handling Acceptance
Address error exception handling is not accepted in a delay slot.
If a multi-cycle instruction is currently being executed, address error exception handling is not
accepted until after execution of that instruction is completed. However, a DIVU or DIVS
instruction can be canceled during execution, allowing address error exception handling to be
accepted.
Address error
exception handling
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
ID
IF
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
EX
MA
MA
Rev. 3.00 Jul 08, 2005 page 445 of 484
MA
IF
Section 8 Pipeline Operation
ID
REJ09B0051-0300
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