R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 71

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOVA
MOVI20
MOVI20S #imm20, Rn
Instruction
@(R0, Rm), Rn
R0, @(disp, GBR)
R0, @(disp, GBR)
R0, @(disp, GBR)
@(disp, GBR), R0
@(disp, GBR), R0
@(disp, GBR), R0
R0, @Rn+
R0, @Rn+
R0, @Rn+
@-Rm, R0
@-Rm, R0
@-Rm, R0
Rm, @(disp12, Rn) 0011nnnnmmmm0001
Rm, @(disp12, Rn) 0011nnnnmmmm0001
Rm, @(disp12, Rn) 0011nnnnmmmm0001
@(disp12, Rm), Rn 0011nnnnmmmm0001
@(disp12, Rm), Rn 0011nnnnmmmm0001
@(disp12, Rm), Rn 0011nnnnmmmm0001
@(disp, PC), R0
#imm20, Rn
0000nnnnmmmm1110 (R0+Rm) → Rn
11000000dddddddd R0 → (disp+GBR)
11000001dddddddd R0 → (disp×2+GBR)
11000010dddddddd R0 → (disp×4+GBR)
11000100dddddddd (disp+GBR) → sign extension
11000101dddddddd (disp×2+GBR) → sign
11000110dddddddd (disp×4+GBR) → R0
0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn
0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn
0100nnnn10101011 R0 → (Rn), Rn + 4 → Rn
0100mmmm11001011 Rm - 1 → Rm, (Rm) → sign
0100mmmm11011011 Rm - 2 → Rm, (Rm) → sign
0100mmmm11101011 Rm - 4 → Rm, (Rm) → R0
0000dddddddddddd
0001dddddddddddd
0010dddddddddddd
0100dddddddddddd
0101dddddddddddd
0110dddddddddddd
11000111dddddddd disp × 4 + PC → R0
0000nnnniiii0000
iiiiiiiiiiiiiiii
0000nnnniiii0001
iiiiiiiiiiiiiiii
Code
→ R0
extension → R0
extension → R0
extension → R0
Rm → (disp+Rn)
Rm → (disp×2+Rn)
Rm → (disp×4+Rn)
(disp+Rm) → sign extension
→ Rn
(disp×2+Rm) → sign
extension → Rn
(disp×4+Rm) → Rn
imm → sign extension → Rn
imm<<8 → sign extension
→ Rn
Operation
Rev. 3.00 Jul 08, 2005 page 55 of 484
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Section 5 Instruction Set
T Bit
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REJ09B0051-0300
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A/
SH2A-
New
FPU
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes