R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 235

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.31
Format
MOV
MOV.W @(disp, PC),Rn
MOV.L @(disp, PC),Rn
Description
Stores immediate data, which has been sign-extended to a longword, into general register Rn.
If the data is a word or longword, table data stored in the address specified by PC + displacement
is accessed. If the data is a word, the 8-bit displacement is zero-extended and doubled.
Consequently, the relative interval from the table can be up to PC + 510 bytes. The PC points to
the starting address of the fourth byte after this MOV instruction. If the data is a longword, the 8-
bit displacement is zero-extended and quadrupled. Consequently, the relative interval from the
table can be up to PC + 1020 bytes. The PC points to the starting address of the fourth byte after
this MOV instruction, but the lowest two bits of the PC are corrected to B'00.
Note
The optimum table assignment is at the rear end of the module or one instruction after the
unconditional branch instruction. If the optimum assignment is impossible for the reason of no
unconditional branch instruction in the 510 byte/1020 byte or some other reason, means to jump
past the table by the BRA instruction are required. By assigning this instruction immediately after
the delayed branch instruction, the PC becomes the "first address + 2".
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×2, ×4) as displacement values.
#imm,Rn
MOV
Immediate Data
Transfer
(disp × 2 + PC) → sign extension → Rn
(disp × 4 + PC) → Rn
Abstract
imm → sign extension → Rn
MOVe immediate data
Rev. 3.00 Jul 08, 2005 page 219 of 484
Code
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
Section 6 Instruction Descriptions
Data Transfer Instruction
REJ09B0051-0300
Cycle
1
1
1
T Bit
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