R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 361

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.3.2
When the result of a previously issued instruction is used as a source, execution is performed after
a wait equivalent to the latency of that instruction. Cases where this applies include the following:
• When waiting for the result of a memory access (see section 8.5, Effect of Memory Load
• When waiting for the result of an FPU operation (see section 8.6, Contention Due to FPU, for
• When waiting for the result of multiplication (see section 8.7, Contention Due to Multiplier,
If the preceding instruction causes contention in these cases, the succeeding instruction must wait
to be executed.
If the succeeding instruction causes contention, the preceding instruction is executed if there is no
other contention.
8.3.3
In the following cases, register contention or flag contention occurs in the same slot.
(1) When the succeeding instruction uses the destination register or flag of the preceding
Figure 8.19 Example of No Contention between Zero-Latency Instruction and Succeeding
CMP/EQ R2,R3
BF
MOV R3,R4
ADD R4,R5
Instruction on Pipeline, for details)
details)
for details)
instruction as a source register or flag (excluding a case where the preceding instruction is a
zero-latency instruction) (figures 8.18 and 8.19)
Details of Contention Due to Wait for Result of Previously Issued Instruction
Details of Register Contention and Flag Contention
Figure 8.18 Example of Flag Contention between Preceding Destination
and Succeeding Source
IF
IF
IF
IF
Instruction
ID
—
ID
ID
EX
ID
EX
EX
EX
Rev. 3.00 Jul 08, 2005 page 345 of 484
Section 8 Pipeline Operation
REJ09B0051-0300