R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 303

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.5.5
Description
When FPSCR.PR = 1, this instruction converts the single-precision floating-point number in
FPUL to a double-precision floating-point number, and stores the result in DRn.
If FPSCR.PR = 0, the instruction is handled as an illegal instruction.
Operation
PR
0
1
void FCNVSD(int n, float *FPUL){
}
void fcnvsd(int n, float *FPUL)
{
Format
—
FCNVSD FPUL, DRn
pc += 2;
clear_cause();
case((FPSCR_PR){
}
case(fpul_type(FPUL)){
}
FCNVSD
Single-Precision
to Double-Precision
Conversion
0:
1:
PZERO :
NZERO :
PINF
NINF
qNaN
sNaN
undefined_operation();
fcnvsd (n, *FPUL);
:
:
:
:
Abstract
—
(double) FPUL → DRn
DR[n>>1] = *FPUL;
qnan(n);
invalid(n);
Floating-point CoNVert
Single to Double precision Floating-Point Instruction
break;
break;
/* reserved */
Code
—
1111nnn010101101 2
Rev. 3.00 Jul 08, 2005 page 287 of 484
/* FCNVSD */
break;
break;
Section 6 Instruction Descriptions
Cycle
—
REJ09B0051-0300
T Bit
—
—