R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 82

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Instruction Set
5.1.7
Table 5.9
FABS
FABS
FADD
FADD
FCMP/EQ FRm, FRn
FCMP/EQ DRm, DRn
FCMP/GT FRm, FRn
FCMP/GT DRm, DRn
FCNVDS DRm, FPUL
FCNVSD FPUL, DRn
FDIV
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FLOAT
FMAC
FMOV
FMOV
FMOV.S @(R0, Rm), FRn
FMOV.D @(R0, Rm), DRn
FMOV.S @Rm+, FRn
FMOV.D @Rm+, DRn
FMOV.S @Rm, FRn
FMOV.D @Rm, DRn
Rev. 3.00 Jul 08, 2005 page 66 of 484
REJ09B0051-0300
Instruction
FRn
DRn
FRm, FRn
DRm, DRn
FRm, FRn
DRm, DRn
FRn
FRn
FRm, FPUL
FPUL,FRn
FPUL,DRn
FR0,FRm,FRn
FRm, FRn
DRm, DRn
Floating-Point Instructions
Floating-Point Instructions
1111nnnn01011101
1111nnn001011101
1111nnnnmmmm0000
1111nnn0mmm00000
1111nnnnmmmm0100
1111nnn0mmm00100
1111nnnnmmmm0101
1111nnn0mmm00101
1111mmm010111101
1111nnn010101101
1111nnnnmmmm0011
1111nnn0mmm00011
1111nnnn10001101
1111nnnn10011101
1111mmmm00011101
1111nnnn00101101
1111nnn000101101
1111nnnnmmmm1110
1111nnnnmmmm1100
1111nnn0mmm01100
1111nnnnmmmm0110
1111nnn0mmmm0110
1111nnnnmmmm1001
1111nnn0mmmm1001
1111nnnnmmmm1000
1111nnn0mmmm1000
Code
|FRn| → FRn
|DRn| → DRn
FRn + FRm → FRn
DRn + DRm → DRn
(FRn=FRm)? 1:0 → T
(DRn=DRm)? 1:0 → T
(FRn>FRm)? 1:0 → T
(DRn>DRm)? 1:0 → T
(float) DRm → FPUL
(double) FPUL → DRn
FRn/FRm → FRn
DRn/DRm → DRn
0 × 00000000 → FRn
0 × 3F800000 → FRn
FRm → FPUL
(float) FPUL → FRn
(double) FPUL → DRn
FR0 × FRm + FRn → FRn
FRm → FRn
DRm → DRn
(R0+Rm) → FRn
(R0+Rm) → DRn
(Rm) → FRn, Rm+ = 4
(Rm) → DRn, Rm+ = 8
(Rm) → FRn
(Rm) → DRn
Operation
Cycles
10
23
1
1
1
6
1
2
1
2
2
2
1
1
1
1
2
1
1
2
1
2
1
2
1
2
Com-
parison
result
Com-
parison
result
Com-
parison
result
Com-
parison
result
T Bit
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―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A/
SH2A-
New
FPU