R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 389

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

System
control
instructions
FPU
load/store
instructions
Type
TRAP
instruction
SLEEP
instruction
FPU load
instructions
FPSCR
load
instructions
FPUL store
instruction
(STS)
FPUL store
instruction
(STS.L)
FPSCR
store
instruction
(STS)
FPSCR
store
instruction
(STS.L)
Category
of Stages
Number
8
7
5
5
4
4
4
4
Execution
States
5
5
1
1
1
1
1
1
Latency
6
0
1
2
3
3
2
2
2
1
• These instruc-
• This instruction
• This instruction
• This instruction
• This instruction
• These instruc-
tions use the
memory access
pipeline.
tions use the
memory access
pipeline.
uses the
multiplication
result read path.
uses the
memory access
pipeline.
uses the
multiplication
result read path.
uses the
memory access
pipeline.
Contention
Rev. 3.00 Jul 08, 2005 page 373 of 484
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Section 8 Pipeline Operation
TRAPA
SLEEP
LDS
LDS.L
LDS
LDS.L
STS
STS.L
STS
STS.L
Instructions
REJ09B0051-0300
#imm
Rm,FPUL
@Rm+,FPUL
Rm,FPSCR
@Rm+,FPSCR
FPUL,Rn
FPUL,@-Rn
FPSCR,Rn
FPSCR,@-Rn