SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 98

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
SFR Definition 26.5. INT_FLAGS
SFR Address = 0xBF
98
Name Reserved
Reset
7:5
Bit
Type
4
3
2
1
0
Bit
Reserved
VOID1_
VOID0_
Name
FLAG
FLAG
ODS_
FLAG
INT1_
FLAG
INT0_
FLAG
R
7
0
Reserved
Read as 0x0. Write has no effect.
Spare Interrupt Flag (can be used freely by the user application software).
Interrupt can be invoked by software only by writing 1 here.
Spare Interrupt Flag (can be used freely by the user application software).
Interrupt can be invoked by software only by writing 1 here.
Set when TX Data Holding Register becomes Empty.
It must be cleared by software BEFORE writing a new byte into the ODS Tx data
register. Hardware will not clear this bit.
Set by Selected GPIO Input by a Selected Edge.
It gets set irrespective of the EINT0 setting. It must be cleared by software. Hard-
ware will not clear this bit.
Set by Selected GPIO Input by a Selected Edge.
It gets set irrespective of the EINT0 setting. It must be cleared by software. Hard-
ware will not clear this bit.
R
6
0
Reserved
R
5
0
VOID1_
FLAG
R/W
Rev. 1.0
4
0
VOID0_
Function
FLAG
R/W
3
0
ODS_
FLAG
R/W
2
0
INT1_
FLAG
R/W
1
0
INT0_
FLAG
R/W
0
0