SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 73

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

5. If the program level is Run then the same boot procedures is followed as for the User device. When
Note: If the Factory or User part is powered up, the part will wait in an infinite loop, consuming power.
Only the Run part executes code in CODE/XDATA RAM automatically. The user can also optionally make
the User part to execute loaded code automatically as described above.
24.6. Error Handling During Boot
At the end of the boot process the bBoot_BootStat byte variable contains the final status of the whole
boot process. Bit field meanings are summarized in SFR Definition 24.1. The user application code should
read that variable and if its value is other then 0x00 or 0x80, then it should decide whether it is safe to run
the application at all. The boot success/fail single bit information is also contained in the BOOT_FLAGS
SFR register for easier access.
24.7. CODE/XDATA RAM Address Map
The 4.5 kB for internal RAM at the address range 0x0000 .. 0x11FF is the main area for the user program
(CODE) and external data (XDATA). It is a unified memory, referred to as CODE/XDATA RAM in this docu-
ment, so both CPU code (CODE) can be executed there and external data (XDATA) can reside there.
External data are the data accessible by MOVX instructions. MOVC instructions can also be used to
access data in that region.
After the boot of a Run part the CPU starts executing code from address 0x0000 in RAM. Therefore, user
code must occupy the beginning of the RAM, followed by the XDATA.
Important: Linker of the user application has to be given proper regions of CODE and XDATA memory,
which are mutually exclusive. Therefore, for example, the user cannot set the CODE region to be 0x0000 ..
0x1000 and XDATA region to be the very same at the same time. One has to specify two non-overlapping
regions for CODE and XDATA in the CODE/XDATA RAM area instead.
The end of the CODE/XDATA RAM is reserved for internal Silicon Labs use. The CODE/XDATA RAM
address space is divided into three parts:
1. User CODE/XDATA .. user application load. The boot process copies the user code and external
2. Factory data values .. variable length. Reserved for Silicon Labs use. The actual beginning of the
3. Boot status variables .. variables in the region 0x11F3 .. 0x11FF are boot status variables set at the end
The visual representation of the RAM is in Figure 24.2. The detailed explanation of the boot control data
variables are in Table 24.1 to SFR Definition 24.1.
loading the User region is done, the user code is run by jumping to the 0x0000 address in
CODE/XDATA RAM. The C2 interface is disabled and the chip can no longer be used with debug chain
and IDE. The Run chip can be opened for retest, but the user has an option to limit Retest access or
lock the chip out completely. See Section “24.11. Retest and Retest Configuration”.
initialized data from NVM to this region.
Silicon Labs reserved area in RAM can be obtained by reading the boot WORD (2 byte) variable
wBoot_DpramTrimBeg. In big endian fashion it contains an address of the first reserved byte of the
RAM. User can use the range 0x0000 .. (wBoot_DpramTrimBeg) - 1 for application CODE and
XDATA
of the boot process to inform the user application about the RAM size available for user application and
about the final status of the boot process.
cannot be cleared. When this bit is 1, then after the Factory and User loads are loaded from
NVM the boot loader enables C2 and runs the user code immediately, without any wait, by
executing long jump to RAM address 0x0000. The IDE can still halt the chip and connect to
it in a usual fashion. From the debug point of view there is no change. This bit corresponds
to the Exe User Boot checkout on the NVM programmer GUI application.
Rev. 1.0
Si4010-C2
73