SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 92

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
26.1. MCU Interrupt Sources and Vectors
The device supports 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic ‘1’. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order, and control bits are summarized in Table 26.1. Refer to the data
sheet section associated with a particular on-chip peripheral for information regarding valid interrupt condi-
tions for the peripheral and the behavior of its interrupt-pending flag(s).
26.2. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 26.1.
26.3. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. Additional clock cycles will be required if a chace miss occurs. If an interrupt is pending when a RETI
is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced
or the new interrupt is of greater priority) is when the CPU is performing an RETI instruction followed by a
DIV as the next instruction. If the CPU is executing an ISR for an interrupt with equal or higher priority, the
new interrupt will not be serviced until the current ISR completes, including the RETI and following instruc-
tion.
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