SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 52

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
17.1. Register Description
SFR Definition 17.1. FC_CTRL
SFR Address = 0x9B
52
Name FC_DONE FC_BUSY FC_DIV_
Reset
4:3
2:0
Bit
Type
7
6
5
Bit
FC_MODE
FC_DONE
FC_BUSY
Reserved
FC_DIV_
Name
[2:0]
SEL
R/W
7
0
Frequency Counter Done.
Counting done, interrupt generation level signal. Must be cleared by software ISR. It
is also cleared if 1 is written to fc_busy, which denotes the start of the next count. Any
value can be written here, so one can invoke interrupt just writing 1 here.
0: Frequency counter is counting
1: Frequency counter done counting, must be cleared by software ISR
Frequency Counter Busy.
Frequency counter is busy counting. Falling edge of the fc_busy signal sets the
FC_DONE=1. Writing 1 to this bit triggers a new FC counting cycle. FC is restartable,
so any Wr 1 to this bit restarts the FC and discards what the FC was currently doing.
0: Frequency counter is not busy, falling edge sets FC_DONE=1
1: Writing 1 restarts the Frequency Counter
Frequency Counter Divider Select.
Selection control of source of clock. It chooses between LC and DIVIDER. If the fre-
quency counter is not enabled, FC_MODE=0, then both signals mentioned above are
in their inactive states.
0: LCOSC
1: DIVIDER
Read as 0x0. Write has no effect.
Frequency Counter Mode Control Register.
000: Frequency counter disabled
001: Interval: clk_ref .. reference clock from GPIO
010: Interval: clk_osc .. undivided output of Low Power Osc (24 MHz)
011: Interval: clk_sys .. system clock, divided output of Low Power Osc
100: Interval: clk_xo .. XO oscillator
101: Reserved
110: Interval: Sleep Timer output
111: Reserved
R/W
6
0
SEL
R/W
5
0
Rev. 1.0
4
Reserved
R
0
Function
3
2
FC_MODE[2:0]
R/W
1
0
0