SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 132

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
34.1. Interrupt Flag Generation
Timer 2 has a single interrupt signal going to interrupt controller. Internally, there are 2 interrupt flags,
TMR2INTH for high half of the timer and TMR2INTL for low half of the timer, which are combined to gener-
ate the final interrupt signal. The low half has a local interrupt flag enable TMR2INTL_EN control bit.
Setting of the interrupt flags depends on the width and functional modes of each timer or its half.


Each of the modes is described in a separate section. There is a clock selection register TMR_CLKSEL
common for both Timer 2 and Timer 3.
132
Wide mode
l
l
Split mode
l
l
Timer mode
Capture mode 
Note: This is an exception when low interrupt flag gets set based on the high half of the timer. This is a
supplemental information for the interrupt handler about the capture, indicating that the 16-bit counter overflew
in between captures.
Timer mode 
Capture mode 
TMR2INTH set if TMR2H overflows 
TMR2INTL set if TMR2L overflows
TMR2INTH set if capture event happens and TMR2H, TMR2L 16-bit value gets captured 
TMR2INTL set if TMR2H overflows.
TMR2INTH set if TMR2H overflows 
TMR2INTL set if TMR2L overflows
TMR2INTH set by capture event when TMR2H gets captured 
TMR2INTL set by capture event when TMR2L gets captured
Figure 34.1. Timer Interrupt Generation
TMR2INTH
TMR2INTL
TMR2INTL_EN
TMR2SPLIT
TMR2H_CAP
TMR2L_CAP
TMR2H_RUN
TMR2L_RUN
Rev. 1.0
Interrupt