SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 88

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
25.2. XREG Registers
The chip contains another set of registers implemented in the XREG memory area. These registers are
located in the XDATA address space, addressable by MOVX instructions only. From CPU perspective it is
a regular external memory.
The advantage of the XREG registers is that they are viewed by the CPU as a regular memory. Therefore,
they can be declared as different data types, structures, array of bytes, and so on. With SFR we only have
special registers and it is not possible to declare them as long integers, for example. On the other hand the
SFR register access is faster and one can use arithmetic and logical operations on them.
Note registers in the XREG regions are aligned at 8, 16, and 32 bit boundaries and they are stored in big
endian fashion. This is to support Keil C compiler, which uses big endian. Note that if the register is, say
23 bits wide, the 32 bits (4 bytes) are allocated for the register and the register is aligned in big endian
fashion.
Therefore, the LSB byte of the register will be at the address <reg_addr> + 3, while the byte directly at the
<reg_addr> is the MSB byte and is empty (read as 0x0), since the register itself is only 23 bits wide.
Table 25.3 shows a memory map of the XREG registers in the external memory space.
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Rev. 1.0