SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 144

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
SFR Definition 34.7. TMR3CTRL
SFR Address = 0xB9
;
144
Name
Reset
Bit
Type
7
6
5
4
3
2
Bit
INTL_EN
TMR3H_
TMR3L_
Name
TMR3
TMR3
TMR3
TMR3
SPLIT
INTH
INTL
CAP
CAP
TMR3
INTH
R/W
7
0
Timer 3 High Byte Interrupt Flag.
Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide
configuration. It gets set when the high half of the timer overflows or there is a cap-
ture event for the high half. This bit is not automatically cleared by hardware.
Timer 3 Low Byte Overflow Flag.
Interrupt flag for the timer low half. It gets set when the low half overflows in timer
mode or by capture event of the low half in capture mode. Software must clear this
bit, hardware will not clear it.
This bit is set when the low half of the timer overflows even if we operate in wide con-
figuration.
When in wide configuration and in capture mode this bit is set when the high half of
the timer overflows. Since in that case the capture event is the same for both halves,
the capture event sets the TMR3INTH interrupt flag. Then this TMR3INTL can be
used as a flag that the timer overflew, serving as an additional 17th timer bit in cap-
ture mode in wide configuration.
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. The overall timer inter-
rupt request signal is : TMR3 interrupt request = TMR3INTH | (TMR3INTL &
TMR3INTL_EN)
Timer 3 Split Mode Enable.
0: Timer operates in wide configuration as 16 bit timer. The low half controls the
whole timer.
1: Timer operates in split configuration. Both halves are controlled independently.
Timer 3 High Byte Capture Mode Enable.
If set then TMR3H high half operates in capture mode if the timer is in split configura-
tion mode. Ignored if the timer operates in wide configuration mode.
Timer 3 Low Byte Capture Mode Enable.
If set then TMR3L low half operates in capture mode if the timer is in split configura-
tion, or the whole timer operates in capture mode if in wide configuration mode.
TMR3
INTL
R/W
6
0
INTL_EN
TMR3
R/W
5
0
SPLIT
TMR3
R/W
Rev. 1.0
4
0
Function
TMR3H_
CAP
R/W
3
0
TMR3L_
CAP
R/W
2
0
TMR3H_
RUN
R/W
1
0
TMR3L_
RUN
R/W
0
0