SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 84

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
24.13. Chip Protection Control Register
The boot process sets the value of the device protection and configuration SFR register, PROT0_CTRL.
The user can read the register and check the programming level of the device as well as protections set to
control access to the NVM and MTP memories and C2 interface. The register is user writable, but once a
value of 1 is written to any of the bits in the register it cannot be written as 0. Only cycling the power to the
part clears the bits, but the boot process will set this register again to the value stored in NVM. Protections
can only be made stronger, not weaker. Writing to this register does not affect the underlying data located
in NVM.
SFR Definition 24.4. PROT0_CTRL
SFR Address = 0xDA
84
Name
Reset
2:0
Bit
Type
7
6
5
4
3
Bit
Reserved
C2_OFF
BLOWN
NVM_
PROT
PROT
NVM_
PROT
NVM_
Name
MTP_
WR_
[2:0]
NVM_
PROT
R/W
7
0
NVM Protection.
Disable NVM access completely. Neither read nor write to NVM is possible. Write 1
sets the bit, write 0 has no effect.
C2 Interface Disable.
Write 1 sets the bit, write 0 has no effect. This bit is reset by the main digital power on
reset. Power has to be cycled to reset this bit or chip has to wake up from shutdown.
If C2 is disabled then the chip is not accessible by a debug chain and not available for
retest.
Reserved.
MTP Protection.
Disable MTP access. If set then MTP will be completely disabled. All reads from MTP
will be 0x00. Write 1 sets the bit, write 0 has no effect.
NVM Write Protection.
If this bit is set the NVM is write protected. However, the value is used only if the chip
program level is Run, NVM_BLOWN=3’b11x. In all other cases the value of this bit is
ignored.
Displays Chip Program Level.
The bits can only be set to 1, write 0 has no effect:
001 .. Factory
011 .. User
111 .. Run
C2_OFF
R/W
6
0
Reserved
R
5
1
PROT
MTP_
Rev. 1.0
R/W
4
0
Function
NVM_
PROT
WR_
R/W
3
0
R/W
2
0
NVM_BLOWN[2:0]
R/W
1
0
R/W
0
0