SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 34

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
The Si4010 has three timing sources. The LCOSC is the most accurate timing source native to the chip.
Each device is factory trimmed and programmed at Silicon Labs to produce a frequency accuracy of better
than ±150 ppm over the temperature range of 0 to + 70 °C and ±250 ppm over the industrial range of –40
to +85 °C. The LCOSC is fitted to a multiple-degree polynomial to compensate for temperature variations
both from the on-chip power amplifier (PA) and also from the external environment. This LCOSC oscillates
around 3.9 GHz and provides the clock (via the DIVIDER) used to modulate the PA for OOK and FSK
transmission. The low power oscillator (LPOSC) is the second timing source and operates at 24 MHz. The
LPOSC is always the source of clocking for the MCU and is turned off only in standby mode. The system
clock is programmable allowing the MCU to operate with lower clock frequencies while waiting between
packets to save power. The RTC and timers 2 and 3 are derived from the LPOSC. The last clock source is
the crystal oscillator (XTALOSC). This crystal oscillator is unused in many customer applications and used
only when a highly accurate carrier frequency is desired. When enabled, it is used before the beginning of
a transmission to correct the frequency of the LCOSC and is then shutdown to save power. An internal fre-
quency counter is implemented in hardware to allow for quick frequency ratio measurements to calibrate
the different clock sources.
The high efficiency PA is a CMOS open drain output driver capable of producing 3.5 Vpk differential output
swing with a supply voltage of 2.2 V or higher. The PA output has 2.4 to 12.5 pF of differential variable
capacitance that is automatically adjusted to resonate the antenna at the start of each packet transmission.
This automatic adjustment is realized with a firmware algorithm in the ROM and some additional hardware
in the PA. Maximum power can be transferred to the inductive antenna load when the antenna and output
driver are at resonance and the real component of the load is equal to the optimum load resistance of
V
/(4/Pi x I
/2) where V
is the peak differential voltage and I
is the tail current of the PA. At higher
pk
tail
pk
tail
resistances the PA is voltage limited and at lower resistances the PA is current limited. The PA tail current
is programmable from 810 uA up to 7.67 mA in 0.25 dB steps and there is a boost current bit that multiplies
the tail current by 1.5 times allowing it to go up to 11.5 mA. With an antenna load resistance of about 500 
an output power of +10 dBm is achievable. Edge rate control is also included for OOK mode to reduce har-
monics that may otherwise violate government regulations.
The on-chip temperature sensor (TEMP SENSOR) measures the internal temperature of the chip and tem-
perature demodulator (TEMP DEMOD) converts the TEMP SENSORs’ output into a binary number repre-
senting temperature and is used to compensate the frequency of the LCOSC when the temperature
changes. Each device's frequency response versus temperature is calibrated in the factory.
The output data serializer (ODS) is responsible for synchronizing the output data to the required data rate
and maintaining a steady data flow when data is available. This block produces the edge rate control for
the PA in OOK mode and the frequency deviation in FSK mode. The block also schedules the power on/off
times of the LCOSC, DIVIDER, and PA to conserve battery power during transmission.
Power management is provided on chip with low-drop-out (LDO) regulators for the internal analog and dig-
ital supplies, VA and VD, respectively. The power-on reset (POR) circuit monitors the power applied to the
chip and generates a reset signal to set the chip into a known state. The bandgap produces voltage and
current references for the analog blocks in the chip and can be shut down when the analog blocks are not
used.
The embedded CIP-51 8051 MCU provides the core functionality of the Si4010. User software has com-
plete control of all peripherals, and may individually shut down any or all peripherals for power savings. 8K
bytes of on-chip one-time programmable NVM memory is available to store the user program and can also
store unique transmit IDs. 128 bits of EEPROM is available for counter or other operations providing non-
volatile storage capability in case of power outages due to battery removal. A library of useful software
functions such as AES encryption, a patented 32-bit counter providing 1M cycles of read/write endurance,
and many other functions are included in the 12 kB of ROM to reduce user design time and code space.
General purpose input/output pins with push button wake-on touch capability are available to further
reduce current consumption.
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Rev. 1.0