SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 133

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

34.2. 16-bit Timer with Auto Reload (Wide Mode)
When TMR2SPLIT=0 and TMR2L_CAP=0, the timer operates as a 16-bit timer with auto reload.
As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the time
reload registers (TMR2RH and TMR2RL) is loaded into the timer register as shown in Figure 34.2, and the
timer High Byte Overflow Flag TMR2INTH (TMR2CTRL.7) is set. If timer interrupts are enabled (see IE
and EIE1 registers), an interrupt will be generated on each timer overflow. Additionally, if timer interrupts
are enabled and the TMR2INTL_EN bit is set (TMR2CTRL.5), an interrupt will be generated each time the
lower 8 bits (TMR2L) overflow from 0xFF to 0x00.
34.3. 16-bit Capture Mode (Wide Mode)
When TMR2SPLIT=0 and TMR2L_CAP=1, the timer operates in a 16-bit capture mode. The capture event
is INT0 for Timer 2 and INT1 for Timer 3. It is the same edge event as programmed to generate external
interrupt INT0 or INT1, respectively. The capture event can be positive edge, negative edge, or both edges
of the GPIO associated with the INT0 and INT1. Capture mode can be used for measurement of time inter-
vals on external signals.
Timer counts up and overflows from 0xFFFF to 0x0000. Each time a capture event is received, the con-
tents of the timer registers (TMR2H:TMR2L) are latched into the timer reload registers
(TMR2RH:TMR2RL). A timer high half interrupt TMR2INTH is generated by capture event. Additionally, the
low byte interrupt flag TMR2INTL is set whenever the timer overflows from 0xFFFF to 0x0000. This addi-
tional information may be used by and application.
Note that the capture event can also generate its own external interrupt on top of the timer interrupt, if
enabled by the application. Also note that if the capture timer is stopped (TMR2L_RUN=0) the capture
event still captures the current counter registers (TMR2H:TMR2L) into the timer reload registers
(TMR2H:TMR2RL) and sets the flag TMR2INTH.
rtc_pulse (100us)
rtc_tick (5.33us)
TMR_CLKSEL
clk_sys/12
clk_sys
0
1
2
3
2
Figure 34.2. Timer 16-bit Mode Block Diagram (Wide Mode)
TMR2L_RUN
TMR2RL
TMR2L
TMR2L overflow
Rev. 1.0
TMR2RH
TMR2H
Reload
TMR2INTH
TMR2INTL
TMR2INTL_EN
TMR2SPLIT
TMR2H_CAP
TMR2L_CAP
TMR2H_RUN
TMR2L_RUN
Si4010-C2
Interrupt
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