SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 6

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
L
F
I S T OF
IGURES
Figure 1.1. Si4010 Block Diagram ............................................................................................ 12
Figure 2.1. Test Block Diagram with 10-Pin MSOP ................................................................. 13
Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator .................................. 14
Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator ..... 14
Figure 1. Si4010 Top Marking .................................................................................................. 16
Figure 2. Si4010 Top Marking .................................................................................................. 17
Figure 7.1. 10-Pin MSOP Package ..........................................................................................22
Figure 7.2. 14-Pin SOIC Package ............................................................................................ 23
Figure 8.1. 10-Pin MSOP Recommended PCB Land Pattern .................................................. 24
Figure 9.1. 14-Pin SOIC Recommended PCB Land Pattern .................................................... 26
Figure 11.1. Functional Block Diagram .................................................................................... 33
Figure 12.1. Simplified PA Block Diagram ............................................................................... 36
Figure 13.1. OOK Timing Example ..........................................................................................40
Figure 13.2. FSK Timing Example ........................................................................................... 40
Figure 17.1. Frequency Counter Block Diagram ...................................................................... 50
Figure 22.1. CIP-51 Block Diagram ..........................................................................................55
Figure 23.1. Address Space Map after the Boot ...................................................................... 65
Figure 24.1. NVM Address Map ............................................................................................... 72
Figure 24.2. CODE/XDATA RAM Address Map ....................................................................... 75
Figure 24.3. Boot Routine Destination CPU Address Space for Copy from NVM .................... 79
Figure 30.1. Device Package and Port Assignments ............................................................. 108
Figure 30.2. GPIO[3:1] Functional Diagram ........................................................................... 110
Figure 30.3. Other GPIO Functional Diagram ........................................................................ 110
Figure 30.4. Push Button Organization in Matrix Mode .......................................................... 113
Figure 30.5. GPIO[5] LED Driver Block Diagram ...................................................................117
Figure 31.1. Output Clock Generator Block Diagram ............................................................. 123
Figure 33.1. RTC Timer Block Diagram .................................................................................128
Figure 34.1. Timer Interrupt Generation .................................................................................132
Figure 34.2. Timer 16-bit Mode Block Diagram (Wide Mode) ................................................ 133
Figure 34.3. Capture 16-bit Mode Block Diagram (Wide Mode) ............................................ 134
Figure 34.4. Two 8-bit Timers in Timer/Timer Configuration (Split Mode) ............................. 135
Figure 34.5. Two 8-bit Timers in Capture/Capture Configuration (Split Mode) ...................... 136
Figure 34.6. Two 8-Bit TImers in Timer/Capture Configuration (Split Mode) ......................... 137
Figure 34.7. Two 8-Bit Timers In Capture/Timer Configuration (Split Mode) ......................... 138
Figure 35.1. 10-pin C2 USB Debugging Adapter Connection to Device ................................ 148
Figure 35.2. 14-Pin C2 ToolStick Connection to Device ........................................................ 150
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Rev. 1.0