SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 65

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

23. Memory Organization
The memory organization of the Si4010 is similar to that of a standard 8051. There are two separate mem-
ory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. However, this device is unique since it has the pro-
gram and data memory spaces combined into one. This is called a unified CODE and XDATA memory.
The device has a standard 8051 program and data address configuration. It includes 256 bytes of internal
data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of
general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128
bytes of internal RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable
as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit address-
able.
Apart from the CPU core related internal memory, the device has the following memories:





See Figure 23.1 for the MCU system memory map:
4.5 kB of RAM .. it can be used both as program CODE and external data XDATA memory
12 kB of ROM .. it holds the Silicon Labs provided API (Application Programming Interface) routines.
The ROM is not readable by the user.
256B hardware control registers mapped to XDATA address space (XREG)
8 kB of one time programmable (OTP) non-volatile memory (NVM)
128 bits of multiple time programmable (MTP) EEPROM. The EEPROM has an endurance of 50,000
updates per bit.
0xAFFF
0xFFFF
0x11FF
0x0000
0x4000
0x8000
RAM 4.5K
ROM 12K
Figure 23.1. Address Space Map after the Boot
XDATA
CODE/
MCU view of unified RAM address space
0xFFFF
0xC000
0x40FF
0x0000
0x4000
0x8000
XDATA
Rev. 1.0
XREG
0x1F
0x2F
0x7F
0xFF
0x00
0x20
0x30
0x80
Direct Addressing
Addressable
Addressing
Registers
Direct &
Inidirect
(DATA)
SFR
Only
Bit
MTP (EEPROM)
NVM (OTP) 8K
DATA/IDATA
128 bits
Si4010-C2
Lower 128 RAM
bytes,
Direct and Indirect
Addressing
Indirect Addressing
Upper 128
RAM
Only
0x80
0xFF
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