SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 120

• Manufacturer Part Number: SI4010-C2-GT
• Description: IC TX 27-960MHZ FSK 3.6V 10MSOP
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GT

• Package / Case: 10-MSOP
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1997-5

Si4010-C2
SFR Definition 30.4. P1CON
SFR Address = 0xA5
SFR Definition 30.5. P2
SFR Address = 0xA0
120
Name
Reset
Name
Reset
7:0 P1CON[7:0]
7:0
Bit
Bit
Type
Type
Bit
Bit
P2[7:0]
Name
Name
R/W
R/W
7
0
7
0
Port 1 Register GPIO[15:8], Bit Addressable.
This bit controls configuration of each corresponding output bit in P1.
0 .. open-drain, pull up resistor connected (see PORT_ROFF)
1 .. push-pull, pull up resistor disabled
If the pin to be input, it must be configured as open-drain and 1 has to be written as
output value to it. Only bits [1:0] corresponding to GPIO[9:8] are used, write to the
rest of the register has no effect, read returns 0 for those bits.
Port 2 Register, Bit Addressable.
It is not a port, but a regular register. This register is used as a page MSB address
byte for XDATA addressing in mode, using the PDATA memory accesses. The sole
purpose for it is to support the PDATA model.
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
Rev. 1.0
4
0
4
0
P1CON[7:0]
P2[7:0]
Function
Function
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0