SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 129

IC TX 27-960MHZ FSK 3.6V 10MSOP

SI4010-C2-GT

Manufacturer Part Number
SI4010-C2-GT
Description
IC TX 27-960MHZ FSK 3.6V 10MSOP
Manufacturer
Silicon Laboratories Inc
Series
EZRadio®r
Type
Crystalless SoC RF Transmitterr
Datasheet

Specifications of SI4010-C2-GT

Package / Case
10-MSOP
Mfg Application Notes
SI4010 Calculator Spreadsheet AppNote
Frequency
27MHz ~ 960MHz
Applications
Garage Openers, RKE, Security Alarms
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
100 kBaud
Power - Output
10dBm
Current - Transmitting
19.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB RAM
Features
8051 MCU Core, Crystal-less Operation
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
27 MHz to 960 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V to 3.6 V
Supply Current
14.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1997-5

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33.1. RTC Interrupt Flag Time Uniformity
Since 100 µs and 200 µs pulse duration is not exactly an integer multiple of the 24 MHz/128 frequency, the
fractional division was used. The 100 µs and 200 µs pulse durations are uniform on average, when
observed over a sufficiently long timer period. Instantaneous time difference in between subsequent
100 µs and 200 µs pulses is not 100 µs or 200 µs, respectively, but fluctuates around those two values.
The pulse trains for 400 µs pulses and longer have a uniform, exact, time periods.
33.2. Register Description
The RTC timer is controlled by the RTC_CTRL SFR register. If there is a need for precise beginning of the
RTC timer period, the internal tick generator can be cleared by writing a bit RTC_TICKCLR in the SYSGEN
register.
The rtc_tick generator runs freely whenever the RTC timer is enabled by RTC_ENA=1. If the user needs
to clear the RTC timer to synchronize it with some event, writing 1 to RTC_CLR will clear the timer, which
keeps running. The RTC rtc_tick generator is not cleared by that event. Therefore, there will be up to
5.33 µs time uncertainty in the calculated time period. Clearing of the RTC rtc_tick generator is achieved
by writing 1 into the RTC_TICKCLR bit in SYSGEN register.
To achieve exact synchronization it is recommended to write 1 into the RTC_TICKCLR, then 1 to
RTC_CLR, followed by another 1 into the RTC_TICKCLR. In assembly using the M_<field> masks 8-bit
mask notation from the supplied assembly include file:
The reason for splitting the clear is that the RTC tick output, rtc_tick can also be selected as a time source
for TMR2 and TMR3, so there is a need to have separate control over the rtc_tick generator clearing.
To get the RTC tick generator running the RTC_ENA=1 must be set. Therefore, even if the RTC interrupt is
not used, the RTC timer must be enabled if the user wants to use the rtc_tick as a clock source for TMR2
or TMR3.
100 µs pulse train .. the 100 µs pulse train consists of rtc_tick time duration of 19, 19, 19, 18 ticks. That
means that 3 subsequent 100 µs pulses has time difference of 19 x rtc_tick periods, which is 19 x
5.33 µs = 101.33 µs. That is followed by a singe duration or 18 x rtc_tick period duration, which is 18 x
5.33 µs = 96 µs. On average, the 100 µs pulse time period is (3 x 19 + 18)/4 x rtc_tick period, which is
18.75 x 5.33 µs = 100 µs exactly.
200 µs pulse train .. for 200 µs the pulse train consists of rtc_tick time duration of 38, 37 ticks. That
means that the pulse train is an alternation train of 38 x 5.33 µs = 202.66 µs and 37 x 5.33 µs =
197.33 µs, when on average the duration is (38 + 37)/2 x 5.33 µs = 200 µs exactly.
orl SYSGEN,
orl RTC_CTLR, #M_RTC_CLR
orl SYSGEN,
#M_RTC_TICKCLR
#M_RTC_TICKCLR
Rev. 1.0
Si4010-C2
129

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