SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 83

IC TX 27-960MHZ FSK 3.6V 10MSOP

SI4010-C2-GT

Manufacturer Part Number
SI4010-C2-GT
Description
IC TX 27-960MHZ FSK 3.6V 10MSOP
Manufacturer
Silicon Laboratories Inc
Series
EZRadio®r
Type
Crystalless SoC RF Transmitterr
Datasheet

Specifications of SI4010-C2-GT

Package / Case
10-MSOP
Mfg Application Notes
SI4010 Calculator Spreadsheet AppNote
Frequency
27MHz ~ 960MHz
Applications
Garage Openers, RKE, Security Alarms
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
100 kBaud
Power - Output
10dBm
Current - Transmitting
19.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB RAM
Features
8051 MCU Core, Crystal-less Operation
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
27 MHz to 960 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V to 3.6 V
Supply Current
14.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1997-5

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24.12. Boot and Retest Protection NVM Control Byte
The boot process monitors the value of an NVM byte called PROT3_CTRL. There is not a corresponding
hardware register to this byte. It is a value in the Factory region at the beginning of NVM. The register
contains Retest protection flags described above and modification of the boot for User part.
Each bit is write 1 once. Once the bit is programmed it cannot be cleared. The bits are programmable
though the checkboxes in the NVM programmer. Once the bit is set, there is no way to monitor the current
status of the bit in the PROT3_CTRL NVM byte on the device.
NVM Byte Definition 24.3. PROT3_CTRL
Name
Reset
Bit
2:3
Type
7
6
5
4
1
0
Bit
USER_CONT
MTP_C2_PR
BOOT_XO_
MEM_C2_
Reserved
Reserved
NVM_C2_
NVM_C2_
PROT
Name
PROT
ENA
PROT
OT
W
7
0
NVM Protection (Disable) When Entering Retest Mode.
This bit corresponds to NVM Disable checkbox on the NVM programmer GUI.
MTP Protection (Disable) When Entering Retest Mode.
This bit corresponds to MTP Disable checkbox on the NVM programmer GUI.
RAM Clearing (Content Protection) When Entering Retest Mode.
This bit corresponds to RAM Clear checkbox on the NVM programmer GUI.
Enable the Crystal Oscillator (XO) at the Beginning of the Boot Process.
This is valid in any device programming level, including Factory . Since it can take up to 10ms
for the XO to stabilize and about 3.6 ms to load 1 kB of data from NVM to RAM, the user may
decide to enable the XO at the beginning of the boot process so the XO will be stabilizing
while the device is going through the boot process to save time in the main application.
This bit corresponds to XO Early Enable checkbox on the NVM programmer GUI.
Reserved.
Run the User Code in User Part after Boot Automatically.
For User programming level only, has no effect in other programming levels. Normally when
the part is programmed as User the user code is loaded from NVM to RAM, but is not
executed automatically. If this bit is set, then the user load is executed automatically after boot.
This bit corresponds to Exe User Boot checkbox on the NVM programmer GUI.
Reserved.
MTP_C2_
PROT
W
6
0
MEM_C2_
PROT
W
5
0
BOOT_XO
_ENA
W
Rev. 1.0
4
0
Function
3
Reserved
0x0
R
2
USER_
Si4010-C2
CONT
W
1
0
Reserved
R
0
0
83

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