NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 151
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Compliant
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Functional Description
5.10.5
Table 57.
Intel
®
ICH8 Family Datasheet
The ICH8 ignores the state of these interrupts in the serial stream, and does not adjust
their level based on the level seen in the serial stream.
Data Frame Format
Table 57
from the ICH8 is AND’d with the PCI input signal. This way, the interrupt can be
signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are
shared).
Data Frame Format
Frame #
Data
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
shows the format of the data frames. For the PCI interrupts (A–D), the output
PCI INTB#
PCI INTC#
PCI INTD#
Interrupt
PCI INTA#
IOCHCK#
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
SMI#
IRQ0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
Clocks Past
Frame
Start
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
2
5
8
Ignored. IRQ13 can only be generated from FERR#
Not attached to PATA (Mobile Only) or SATA logic
Not attached to PATA (Mobile Only) or SATA logic
Ignored. IRQ0 can only be generated via the internal
8524
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
Ignored. IRQ8# can only be generated internally.
Same as ISA IOCHCK# going active.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
Comment
151
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