NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 753

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NH82801HEM S LB9B

Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LB9B

Lead Free Status / RoHS Status
Compliant
Serial Peripheral Interface (SPI)
20.1.9
20.1.10
Intel
®
ICH8 Family Datasheet
FREG1—Flash Region 1 (BIOS Descriptor) Register
(
Memory Address:SPIBAR + 58h
Default Value:
FREG2—Flash Region 2 (ME) Register
(
Memory Address:SPIBAR + 5Ch
Default Value:
31:29
28:16
15:13
12:0
31:29
28:16
15:13
12:0
SPI Memory Mapped Configuration Registers
SPI Memory Mapped Configuration Registers
Bit
Bit
Reserved
Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 1
Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
Reserved
Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 1
Base.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
Reserved
Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 2
Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
Reserved
Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 2 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base.
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
)
)
RO
32 bits
RO
32 bits
753

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