NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 436

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

10.1.7
10.1.8
10.1.9
436
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Default Value:
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Default Value:
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h–1Ah
Default Value:
23:16
15:8
6:0
7:0
7:3
2:0
Bit
Bit
Bit
7
Multi-Function Device (MFD) — RO. A 0 indicates a single function device
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge in this case.
Subordinate Bus Number (SBBN) — R/W. This field indicates the highest PCI bus
number below the bridge.
Secondary Bus Number (SCBN) — R/W. This field indicates the bus number of PCI.
Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-ICH8
system, programmable PBN allows an ICH8 to be located on any bus. System
configuration software is responsible for initializing these registers to appropriate
values. PBN is not used by hardware in determining its bus number.
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
Specification, Revision 1.0a.
Reserved
00h
01h
000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
RO
8 bits
RO
8 bits
R/W, RO
24 bits
Intel
®
ICH8 Family Datasheet