NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 587
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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EHCI Controller Registers (D29:F7, D26:F7)
15.1.3
Intel
®
ICH8 Family Datasheet
PCICMD—PCI Command Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 04h
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit (D29:F7, D26:F7:06h, bit 3) is not
affected by the interrupt enable.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR#
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the ICH8 to act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory
Space registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F7,
I/O Space Enable (IOSE) — RO. Hardwired to 0.
when it receive a completion status other than “successful” for one of its DMA-
initiated memory reads on DMI (and subsequently on its internal interface).
D26:F7:10h) for USB 2.0 should be programmed before this bit is set.
0000h
–
05h
Description
Attribute:
Size:
R/W, RO
16 bits
587
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