NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 458

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NH82801HEM S LB9B

Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LB9B

Lead Free Status / RoHS Status
Compliant
11.1.23
458
SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1)
Address Offset:
Default Value:
7:4
3:2
Bit
1
0
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 1.
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 0.
48h
00h
Description
Attribute:
Size:
IDE Controller Registers (D31:F1) (Mobile Only)
R/W
8 bits
Intel
®
ICH8 Family Datasheet

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