NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 846
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Table 172.
846
Power Sequencing and Reset Signal Timings
NOTES:
1.
Sym
t200
t201
t202
t203
t204
t205
t206
t207
t208
t209
t211
t212
t213
t214
t215
t217
t218
t219
t228
t229
V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must
power down after Vcc3_3, or before Vcc3_3 within 0.7 V.
VccRTC active to RTCRST# inactive
V5REF_Sus active to VccSus3_3 active
VccSus3_3 active to VccSus1_05 active
VccRTC supply active to VccSus supplies
active
VccSus supplies active to LAN_RST#
inactive, RSMRST# inactive
VccSus3_3 active to VccSus1_5 active
VccLAN3_3 active to VccLAN1_05 active
VccCL3_3 active to VccCL1_05 active
VccCL3_3 active to VccCL1_5 active
V5REF active to Vcc3_3 active
Vcc1_5 active to V_CPU_IO active
VRMPWRGD active to PWROK active
VccSus supplies active to Vcc supplies
active
Vcc supplies active to PWROK
Note: PWROK assertion indicates that
PCICLK has been stable for at least 1 ms.
Vcc active to STPCLK# and CPUSLP#
(Desktop only) inactive
PWROK and VRMPWRGD active to
SUS_STAT# inactive and Processor I/F
signals latched to strap value
SUS_STAT# inactive to PLTRST# inactive
PLTRST# assertion to VccGLANPLL
inactive for platforms using ICH8
integrated GbE LAN
HDA_RST# active low pulse width
HDA_RST# inactive to HDA_BIT_CLK
startup delay
Parameter
162.8
Min
200
18
10
99
32
—
—
—
—
—
—
—
0
0
0
3
0
2
1
Max
50
38
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
–
RTCCLK
RTCCLK
Intel
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
us
ns
Electrical Characteristics
—
—
—
—
μs
®
ICH8 Family Datasheet
Fig
39
40
39
40
39
40
39
40
39
40
39
39
40
42
40
39
39
40
42
43
40
42
43
40
42
43
45
40
42
43
45
Notes
5, 10
10
11
1
2
3
9
6
7
8
1
4
3
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