NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 416
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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9.9
Table 116.
9.9.1
416
System Management TCO Registers (D31:F0)
The TCO logic is accessed via registers mapped to the PCI configuration space (Device
31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC
Device 31:Function 0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, PMBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the following
sections.
TCO I/O Register Address Map
TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address:
Default Value:
Lockable:
15:10
TCOBASE
+ Offset
0Ah–0Bh
0Ch–0Dh
00h–01h
04h–05h
06h–07h
08h–09h
12h–13h
14h–1Fh
9:0
Bit
02h
03h
0Eh
0Fh
10h
11h
Reserved
TCO Timer Value — R/W. Reading this register will return the current count of the TCO
timer. Writing any value to this register will reload the timer to prevent the timeout.
TCO_MESSAGE1,
TCO_MESSAGE2
TCO_DAT_OUT
SW_IRQ_GEN
TCO_DAT_IN
TCO_WDCNT
Mnemonic
TCO1_CNT
TCO1_STS
TCO2_STS
TCO2_CNT
TCO_TMR
TCO_RLD
TCOBASE +00h
0000h
No
—
—
—
TCO Timer Reload and Current
Value
TCO Data In
TCO Data Out
TCO1 Status
TCO2 Status
TCO1 Control
TCO2 Control
TCO Message 1 and 2
Reserved
Software IRQ Generation
Reserved
TCO Timer Initial Value
Reserved
Watchdog Control
Register Name
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
16-bit
Core
Default
0000h
0000h
0000h
0000h
0008h
0004h
Intel
00h
00h
03h
00h
00h
—
—
—
®
ICH8 Family Datasheet
(special), R/
R/W, R/WC
R/WC, RO
Type
R/W,
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WC
—
—
—
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