NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 517
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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SATA Controller Registers (D31:F2)
12.4.1.4
Intel
®
ICH8 Family Datasheet
PI—Ports Implemented Register (D31:F2)
Address Offset: ABAR + 0Ch–0Fh
Default Value:
This register indicates which ports are exposed to the ICH8. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. For ports that are not available, software must not read or write to registers within
that port.
(Desktop
(Desktop
(Desktop
(Mobile
(Mobile
(Mobile
Only)
Only)
Only)
Only)
Only)
Only)
31:6
Bit
5
5
4
4
3
3
2
1
0
Reserved. Returns 0.
Ports Implemented Port 5 (PI5) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 5 (PI5) — RO.
0 = The port is not implemented.
Ports Implemented Port 4 (PI4) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 4 (PI4) — RO.
0 = The port is not implemented.
Ports Implemented Port 3 (PI3) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 3 (PI3) — RO.
0 = The port is not implemented.
Ports Implemented Port 2 (PI2)— R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 1 (PI1) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 0 (PI0) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
00000000h
Description
Attribute:
Size:
R/WO, RO
32 bits
517
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