NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 663
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Intel
17.1.45
17.1.46
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
VCiCTL—VCi Resource Control Register
(Intel
Address Offset: 120h–123h
Default Value:
VCiSTS—VCi Resource Status Register
(Intel
Address Offset: 126h–127h
Default Value:
30:27
26:24
23:20
19:17
15:8
15:2
7:0
Bit
Bit
31
16
1
0
VCi Enable — R/W.
0 = Disabled
1 = Enabled
NOTE: This bit is not reset on D3
Reserved.
VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by
the ICH8 hardware, but it is R/W to avoid confusing software.
Reserved.
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
devices
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint
devices
Reserved.
TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi
resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1]
are implemented as R/W bits. This field is not used by the ICH8 hardware, but it is R/W
to avoid confusing software.
Reserved.
VCi Negotiation Pending — RO. Does not apply. Hardwired to 0.
Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
0000h
HOT
Description
Description
to D0 transition; however, it is reset by PLTRST#.
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
RO
16 bits
663
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