NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 423
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 423 of 890
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
9.10
Table 117.
Intel
®
ICH8 Family Datasheet
GPIOBASE
+ Offset
00h–03h
04h–07h
08h–0Bh
0Ch–0Fh
10h–13h
14h–17h
18h–1Bh
1Ch–1Fh
30h–33h
34h–37h
38h–3Bh
3Ch–3Fh
General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte
I/O space. The base offset for this space is selected by the GPIOBASE register.
Registers to Control GPIO Address Map
20–23h
24–27h
28–2Bh
2C–2Fh
GP_SB_CMDSTS[31:0]
GP_SER_BLINK[31:0]
GP_SB_DATA[31:0]
GPIO_USE_SEL2
Override (HIGH)
GPIO_USE_SEL
Override (LOW)
GPIO_USE_SEL
GPIO_USE_SEL
GP_IO_SEL2
GPO_BLINK
Mnemonic
GP_IO_SEL
GP_LVL2
GPI_INV
GP_LVL
—
—
—
GPIO Use Select
GPIO Input/Output Select
Reserved
GPIO Level for Input or Output
GPIO Use Select Override Low
Reserved
GPIO Blink Enable
GP Serial Blink [31:0]
GP Serial Blink Command Status
[31:0]
GP Serial Blink Data [31:0]
Reserved
GPIO Signal Invert
GPIO Use Select 2 [63:32]
GPIO Input/Output Select 2
[63:32]
GPIO Level for Input or Output 2
[63:32]
GPIO Use Select Override High
Register Name
(Desktop) /
00000000h
00040000h
00000000h
00000800h
00000000h
00000000h
(Desktop) /
00AA0003h
00000000h
197E55FFh
E0EA7FFFh
02FE8000h
000100FFh
000100FEh
00550FF0h
197F75FFh
Default
(Mobile)
(Mobile)
—
—
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
423
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