NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 316

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

8.1.15
8.1.16
8.1.17
8.1.18
316
ERBA—Expansion ROM Base Address Register
(Gigabit LAN—D25:F0)
Address Offset: 30h
Default Value:
CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h
Default Value:
INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh
Default Value:
MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh
Default Value:
15:8
31:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first
entry in the capabilities list is at C8h in configuration space.
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the Gb LAN
controller.
01h = The Gb LAN controller implements legacy interrupts on INTA.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
Expansion ROM Base Address (ERBA) — RO. This register is used to define the address
and size information for boot-time access to the optional FLASH memory. If no Flash
memory exists this register reports 00000000h.
See bit description
C8h
0100h
00h
–
33h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Gigabit LAN Configuration Registers
RO
32 bits
R0
8 bits
R/W, RO
16 bits
RO
8 bits
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ICH8 Family Datasheet