NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 778
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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20.3.2
778
HSFS—Hardware Sequencing Flash Status Register
(
Memory Address:GLBAR + 04h
Default Value:
GbE LAN Memory Mapped Configuration Registers
12:6
4:3
Bit
15
14
13
5
2
Flash Configuration Lock-Down (FLOCKDN)— R/W/L. When set to 1, those Flash
Program Registers that are locked down by this FLOCKDN bit cannot be written. Once
set to 1, this bit can only be cleared by a hardware reset.
Hardware reset is initiated by one of the following resets:
Flash Descriptor Valid (FDV)— RO. This bit is set to a 1 if the Flash Controller read
the correct Flash Descriptor Signature.
If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing
registers, but must use the software sequencing registers. Any attempt to use the
Hardware Sequencing registers will result in the FCERR bit being set.
Flash Descriptor Override Pin Strap Status (FDOPSS)— RO. This bit reflects the
value the Flash Descriptor Override Pin-Strap.
1 = No override
0 = The Flash Descriptor Override strap is set
Reserved
SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
and clears this bit so that software can determine when read data is valid and/or when
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector
size for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 KB
10 = Reserved for future use
11 = 64 KB
made to access the BIOS region using the direct access method or an access to the
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
an access security violation. This bit is cleared by software writing a 1.
Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
non-ME systems.
ME enabled systems.
0000h
Description
Size:
Attribute:
Serial Peripheral Interface (SPI)
RO, R/WC, R/WL
16 bits
)
Intel
®
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