NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 459

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1) (Mobile Only)
11.1.24
Note:
Intel
®
ICH8 Family Datasheet
SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset:
Default Value:
For FAST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to
for details.
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Bit
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Reserved
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these
bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP
(RP) time is also determined by the setting of these bits.
Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these
bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP
(RP) time is also determined by the setting of these bits.
00 = CT 4 clocks,
01 = CT 3 clocks,
10 = CT 2 clocks,
00 = CT 4 clocks,
01 = CT 3 clocks,
10 = CT 2 clocks,
11 = Reserved
11 = Reserved
(33 MHz clk)
(33 MHz clk)
RP 6 clocks
RP 5 clocks
RP 4 clocks
RP 6 clocks
RP 5 clocks
RP 4 clocks
PCB1 = 0
PCB1 = 0
4Ah
0000h
–
4Bh
01 = CT 3 clocks,
10 = CT 2 clocks,
01 = CT 3 clocks,
10 = CT 2 clocks,
00 = Reserved
11 = Reserved
00 = Reserved
11 = Reserved
(66 MHz clk)
(66 MHz clk)
RP 8 clocks
RP 8 clocks
RP 8 clocks
RP 8 clocks
Description
PCB1 = 1
PCB1 = 1
Attribute:
Size:
16 bits
R/W
01 = CT 3 clocks,
01 = CT 3 clocks,
FAST_PCB1 = 1
FAST_PCB1 = 1
(133 MHz clk)
(133 MHz clk)
00 = Reserved
10 = Reserved
11 = Reserved
00 = Reserved
10 = Reserved
11 = Reserved
RP 16 clocks
RP 16 clocks
Section 5.15.4
459