NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 543

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F5)
13.1.6
13.1.7
13.1.8
13.1.9
Intel
®
ICH8 Family Datasheet
PI—Programming Interface Register (SATA–D31:F5)
Address Offset: 09h
Default Value:
SCC—Sub Class Code Register (SATA–D31:F5)
Address Offset: 0Ah
Default Value:
BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5)
Address Offset: 0Bh
Default Value:
PMLT—Primary Master Latency Timer Register
(SATA–D31:F5)
Address Offset: 0Dh
Default Value:
6:4
7:0
7:0
7:0
Bit
Bit
Bit
Bit
7
3
2
1
0
This read-only bit is a 1 to indicate that the ICH8 supports bus master operation
Reserved. Will always return 0.
Secondary Mode Native Capable (SNC) — RO.
0 = Secondary controller only supports legacy mode. This bit will always return ‘0’
Secondary Mode Native Enable (SNE) — R/W / RO.
Determines the mode that the secondary channel is operating in.
1 = Secondary controller operating in native PCI mode. This bit will always return ‘1’
Primary Mode Native Capable (PNC) — RO.
0 = Primary controller only supports legacy mode. This bit will always return ‘0’
Primary Mode Native Enable (PNE) — RO.
Determines the mode that the primary channel is operating in.
1 = Primary controller operating in native PCI mode. This bit will always return ‘1’
Interface (IF) — RO.
This controller only supports IDE programming interface and is only 01h.
Base Class Code (BCC) — RO.
01h = Mass storage device
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
85h
01h
01h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
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