NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 678

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

17.2.14
678
INTSTS—Interrupt Status Register
(Intel
Memory Address:HDBAR + 24h
Default Value:
29:8
7:0
Bit
31
30
Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in
this register.
NOTE: This bit is not affected by the D3
Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
1 = Interrupt condition occurred due to a Response Interrupt, a Response Buffer
NOTES:
1.
2.
Reserved
Stream Interrupt Status (SIS) — RO.
1 = Interrupt condition occurred on the corresponding stream. This bit is an OR of all of
NOTE: These bits are set regardless of the state of the corresponding interrupt enable
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0: input stream 1
Bit 1: input stream 2
Bit 2: input stream 3
Bit 3: input stream 4
Bit 4: output stream 1
Bit 5: output stream 2
Bit 6: output stream 3
Bit 7: output stream 4
®
High Definition Audio Controller—D27:F0)
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
interrupt status bits for this register.
the stream’s interrupt status bits.
This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
This bit is not affected by the D3
bits.
00000000h
Intel
®
Description
High Definition Audio Controller Registers (D27:F0)
HOT
HOT
Attribute:
Size:
to D0 transition.
to D0 transition.
RO
32 bits
Intel
®
ICH8 Family Datasheet