NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 706

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

18.1.15
706
SSTS—Secondary Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Eh–1Fh
Default Value:
10:9
4:0
Bit
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = No error.
1 = The port received a poisoned TLP.
Received System Error (RSE) — R/WC.
0 = No error.
1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.
Received Master Abort (RMA) — R/WC.
0 = Unsupported Request not received.
1 = The port received a completion with “Unsupported Request” status from the device.
Received Target Abort (RTA) — R/WC.
0 = Completion Abort not received.
1 = The port received a completion with “Completion Abort” status from the device.
Signaled Target Abort (STA) — R/WC.
0 = Completion Abort not sent.
1 = The port generated a completion with “Completion Abort” status to the device.
Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base
Specification.
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions below did not occur
1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of
Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base
Specification.
Reserved
Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.
Reserved
• Port receives completion marked poisoned.
• Port poisons a write request to the secondary side.
the following two conditions occurs:
0000h
.
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/WC
16 bits
Intel
®
ICH8 Family Datasheet