NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 683
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Intel
17.2.25
17.2.26
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
RIRBUBASE—RIRB Upper Base Address Register
(Intel
Memory Address:HDBAR + 54h
Default Value:
RIRBWP—RIRB Write Pointer Register
(Intel
Memory Address:HDBAR + 58h
Default Value:
31:0
14:8
7:0
Bit
Bit
15
RIRB Upper Base Address — R/W. This field provides the upper 32 bits of the
address of the Response Input Ring Buffer. This register field must not be written when
the DMA engine is running or the DMA transfer may be corrupted.
RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB
Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write
Pointer or else DMA transfer may be corrupted.
NOTE: This bit is always read as 0.
Reserved.
RIRB Write Pointer (RIRBWP) — RO. This field indicates the last valid RIRB entry written
by the DMA controller. Software reads this field to determine how many responses it
can read from the RIRB. The value read indicates the RIRB Write Pointer offset in
2 DWord RIRB entry units (since each RIRB entry is 2 DWords long); supports up to
256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the DMA
engine is running.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W, RO
16 bits
683
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