NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 784

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

20.3.11
Note:
20.3.12
Note:
784
PR0—Protected Range 0 Register
(
Memory Address:GLBAR + 74h
Default Value:
This register can not be written when the FLOCKDN bit is set to 1.
PR1—Protected Range 1 Register
(
Memory Address:GLBAR + 78h
Default Value:
This register can not be written when the FLOCKDN bit is set to 1.
28:16
28:16
30:29
14:13
30:29
14:13
GbE LAN Memory Mapped Configuration Registers
GbE LAN Memory Mapped Configuration Registers
12:0
12:0
Bit
Bit
31
15
31
15
Write Protection Enable: — R/WL. When set, this bit indicates that the Base and
Limit fields in this register are valid and that writes and erases directed to addresses
between them (inclusive) must be blocked by hardware. The base and limit fields are
ignored when this bit is cleared.
Reserved
Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable: — R/WL. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
Reserved
Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
Write Protection Enable: — R/WL. When set, this bit indicates that the Base and
Limit fields in this register are valid and that writes and erases directed to addresses
between them (inclusive) must be blocked by hardware. The base and limit fields are
ignored when this bit is cleared.
Reserved
Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable: — R/WL. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
Reserved
Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
Serial Peripheral Interface (SPI)
R/WL
32 bits
R/WL
32 bits
)
)
Intel
®
ICH8 Family Datasheet