NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 389
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 389 of 890
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LPC Interface Bridge Registers (D31:F0)
9.8.1.11
9.8.1.12
Note:
Intel
®
ICH8 Family Datasheet
QRT_CNT2 (PM—D31:F0): Quick Resume Technology Control 2
Register (Intel
Offset Address: B3h
Default Value:
Lockable:
Power Well:
GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0)
Offset Address: B8h – BBh
Default Value:
Lockable:
GPIOs that are not implemented will not have the corresponding bits implemented in
this register.
31:30
7:1
Bit
5:4
3:2
1:0
Bit
0
Reserved
QRT_EN—R/W: This bit enables Quick Resume Technology
0 = QRT Disabled
1 = QRT Enabled
When this bit is 0, the R/W bits of QRT Control Registers (QRT_CNT1, EL_CNT2)
scratchpad with no effect on hardware functions. Also, WO bits have no effect on
hardware functions.
BIOS software is expected to set this bit after booting. Default value for this bit is 0.
GPIO15 Route — R/W. See bits 1:0 for description.
GPIO2 Route — R/W. See bits 1:0 for description.
GPIO1 Route — R/W. See bits 1:0 for description.
GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the
GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
00h
No
RTC
00000000h
No
®
ICH8DH Only)
Same pattern for GPIO14 through GPIO3
Attribute:
Size:
Usage:
Description
Description
Attribute:
Size:
Power Well:
R/W
8-bit
Quick Resume Technology
R/W
32-bit
Resume
389
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