NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 567

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
14.1.3
Intel
®
ICH8 Family Datasheet
PCICMD—PCI Command Register (USB—D29:F0/F1/F2,
D26:F0/F1)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable. The function is able to generate its interrupt to the interrupt controller.
1 = Disable. The function is not capable of generating interrupts.
NOTE: The corresponding Interrupt Status bit is not affected by the interrupt enable.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
0 = Disable
1 = Enable. ICH8 can act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable
1 = Enable accesses to the USB I/O registers. The Base Address register for USB should
be programmed before this bit is set.
04h
0000h
–
05h
Description
Attribute:
Size:
R/W, RO
16 bits
567