NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 306
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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7.1.72
306
CG—Clock Gating (Mobile Only)
Offset Address: 341C–341Fh
Default Value:
29:28
18:17
Bit
31
30
27
26
25
24
23
22
21
20
19
16
Legacy (LPC) Dynamic Clock Gate Enable — R/W.
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
PATA Dynamic Clock Gate Enable — R/W.
0 = PATA Dynamic Clock Gating is Disabled
1 = PATA Dynamic Clock Gating is Enabled
USB UHCI Dynamic Clock Gate Enable — R/W.
0 = USB UHCI Dynamic Clock Gating is Disabled
1 = USB UHCI Dynamic Clock Gating is Enabled
0 = Reserved
1 = Reserved
Reserved
SATA Port 2 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 2 Dynamic Clock Gating is Disabled
1 = SATA Port 2 Dynamic Clock Gating is Enabled
SATA Port 1 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 1 Dynamic Clock Gating is Disabled
1 = SATA Port 1 Dynamic Clock Gating is Enabled
SATA Port 0 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 0 Dynamic Clock Gating is Disabled
1 = SATA Port 0 Dynamic Clock Gating is Enabled
LAN Static Clock Gating Enable (LANSCGE) — R/W.
0 = LAN Static clock gating is disabled
1 = LAN Static clock gating is enabled when the LAN Disable bit is set in the Function
High Definition Audio Dynamic Clock Gate Enable — R/W.
0 = High Definition Audio Dynamic Clock Gating is Disabled
1 = High Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable — R/W.
0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
Reserved
PCI Dynamic Gate Enable — R/W.
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
Disable SUS Well register.
00000000h
Description
Attribute:
Size:
Chipset Configuration Registers
R/W, RO
32-bit
Intel
®
ICH8 Family Datasheet
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